mycontroller – RAM
July 5, 2007 Leave a comment
This is part of a project to build a complete, functional, extremely basic microcontroller. It is built using multimedia logic.
This is a functional subsystem that manages a small RAM in our architecture speed across 2 128 byte memory addresses.
All the Input and output can be viewed from the first page.
The tristate devices on the input (address and data pages) are probably not necessary, and on the solution I saw were not there. However, they were the only way I could think of to have an active disconnect rather than a zero or one.
There is a lot of complexity added because of this.
Also, there would have been additional complexity that would have been added if the read were not active. But because of the email sent earlier modifying the specifications, this is not the case and I have left the read in active mode (if you are not writing, you are reading).
Here is a link to the source.