Download the mmlogic schematic here, the memfile here, and the cache file here.
The clock is run at a very slow speed so you can see what is happening. I didn’t bother to stop the memory/cache from outputting, so there is a constant read.
The input is a memory address, which is fetched from Cache (if the data is in Cache) or RAM (if the data is not in Cache).
The part of the system not being used (RAM or cache) is always doing stuff, but this system just throws it away if it is not relevant, and keeps it if it is.
The Cache is done using a direct addressing scheme. The addresses are stored in the “higher” half of the addresses. For example, the data at 0000xxxx in the cache has the address in RAM stored at (in the cache) 0001xxxx.
At first, the program begins. Because there is a default read, the instruction is to read 00000000 out of RAM.
The Controller will check to see if this value is in cache (page 4). It checks this using an ALU and zero flag. It is not, so memwrite (the zero flag output) will be set to +1. This indicates to output the value from RAM. The value is output from RAM, and put in cache.
Because there is a constant read, the value at RAM 00000000 is read again, but this time, it is in cache. The ALU will compare the value at Cache 00010000 with the address, and they are equal, so ZF flag is set.
Flip any switch, the process above repeats.
Flip the switch back so the address is once again 00000000, and notice that the value is only read from cache.
The logic analyzer will be a mess, because of my use of oscillators. I recommend debugging by sight and LEDs.
The oscillators function as a system clock. This is a synchronous system.
The cache writing flag is oscillated only if the memwrite flag indicates that there must be a cache write (if the system had to retrieve something from RAM)
The control address oscillator is constantly moving back and forth between where the data is stored and where the address is stored in cache. It oscillates at a slower speed than the write oscillator.